This course provides comprehensive training in functional verification of digital and SoC designs. Learners gain hands-on experience with SystemVerilog, UVM, assertion-based verification, and coverage-driven methodologies used in semiconductor industries.
Fundamental Topics
Covers verification basics, simulation principles, testbenches, functional correctness, assertion concepts, and verification methodologies.
Verification fundamentals
Testbench architecture
Assertions basics
Intermediate Topics
Focuses on constrained-random testing, coverage analysis, formal verification, hardware description languages, and verification planning techniques.
SystemVerilog
UVM methodology
Coverage-driven verification
Advanced Topics
Includes system-level verification, UVM methodology, advanced assertions, equivalence checking, low-power verification, and automation strategies.
Formal verification
Low-power verification
SoC-level verification
Course Outcomes
Enable students to design, implement, and validate hardware systems ensuring correctness, reliability, and compliance efficiently.